During typical semiconductor manufacturing processes, a plurality of integrated circuits are formed as individual dice on a semiconductor wafer. Each semiconductor wafer generally has hundreds to thousands of individual dice formed thereon. Once the dice are formed on a semiconductor wafer, the dice are then tested to determine which dice are functional and which dice are not functional. In most testing procedures, each die is probed using probe equipment while the dice are still on the wafer. This step is also known as “wafer sort.”
The purpose of the wafer-level probe test is to determine, as early as possible in the manufacturing process, whether each individual die is defective or not. The earlier a defective die is detected, the less time and expense that is wasted on further processing of defective dice. That is, if it is determined that a detected defect cannot be repaired, the time and expense of completing a chip assembly will not be expended. After the wafer-level testing, the functional dice are then packaged, and generally the packaged part is tested again to ensure that no defects were introduced during packaging. Various techniques have been developed for performing wafer-level testing, such as those described further below, and as is known in the art similar techniques may also be used for testing a packaged device.
In typical semiconductor testing, the device under test (DUT) (which may be referred to as “circuitry under test” (CUT) and is intended to encompass a device under test on a wafer as well as a packaged device) receives a set of input stimuli from automatic test equipment (ATE) arranged external to the DUT, after which the ATE observes the DUT outputs. In general, the correct expected outputs of the DUT are stored in the ATE memory, and the ATE compares all of the output bits received from the DUT against the stored expected bit values to determine whether the DUT is functioning properly (e.g., whether the DUT is generating the expected output values responsive to the input values). Thus, a DUT (e.g., a device on a wafer or a packaged device) may be communicatively coupled to an external ATE, and such ATE may input test stimuli thereto and receive and analyze responses therefrom. As described further below, circuitry may be included on the DUT, which may, for example, generate a signature corresponding to the DUT's response to the input stimuli, and such signature may be output to the ATE. While much of the testing techniques described herein are described as testing a DUT that is on a wafer (i.e., wafer-level testing), it should be recognized that similar techniques may typically also be used for testing a packaged device.
In the case of wafer-level testing, a probe may be brought into contact with one or more bonding pads of a die in order to communicate signals (e.g., a test pattern) to the die and to receive the signals output by the die responsive to the input signals. The probe is typically communicatively coupled to an external ATE that is operable to generate the signals to be input to a die and to evaluate the signals output by the die in order to determine whether the die is functioning properly. Dice on a wafer may be tested serially (e.g., by contacting each die with the probe in series) or in parallel.
Traditional testing techniques of the existing art require an undesirably large amount of memory on the ATE utilized for the testing, which undesirably increases the cost of the ATE and the resulting product. For instance, sufficient data storage that is communicatively coupled to the ATE is generally required for storage of at least the following information for a testing technique: 1) input vector data, 2) output vector data, and 3) mask vector data. In general, the input vector data stored at the ATE comprises the data that is used as stimuli for inputs to the DUT (e.g., test pattern data), and the output vector data comprises the expected output data of the DUT given the input vector data, which is used for comparison with the actual output data of the DUT responsive to the input vector data to determine whether the DUT is functioning properly. Generally, the mask vector data comprises data designating which of the bits of the expected output data actually need to be compared to the received outputs of the DUT, e.g., the mask vector data maps the expected output data to the actual output data received from the DUT, as in certain configurations all of the output bits of the DUT may not be compared with expected output data (e.g., certain non-deterministic bits, or “don't care/unknown bits”, may exist, the value of which is not relevant to the correct functioning of the DUT).
Such input vector data, output vector data, and mask vector data for a testing technique may consume an undesirably large amount of data storage space on the ATE. Further, as the comprehensiveness of a testing technique is increased and/or as the complexity of the device to be tested increases, the amount of data storage space consumed on the ATE for this vector data is likely also increased. For example, traditional testing techniques of the existing art commonly use approximately 400 to 800 bits per gate of the DUT being tested. Of course, depending on the complexity of the DUT and/or the comprehensiveness of the testing technique implemented (e.g., the number of flip-flops on the DUT being tested and/or the number of input test patterns utilized), the size of the input vector data, output vector data, and/or mask vector data may vary from testing technique to testing technique (but, in current ATE architectures, for each output bit a mask bit is required such that mask vector memory is equal to the output vector memory). Embodiments of the present invention breaks this barrier, thus enabling reduction in the amount of data storage required on an ATE for a test.
In general, it is desirable to minimize the amount of data storage required on the ATE for implementing a testing technique. Several solutions have been proposed in the existing art for reducing the ATE's data storage requirements for implementing a testing technique, and more particularly, for reducing the ATE's storage requirements for storing the output vector data for a testing technique. The most pervasive techniques for minimizing the amount of data storage required on an ATE for storing output vector data are vector set truncation techniques and on-chip signature analysis techniques, which are described further below.
One popular technique for minimizing the amount of data storage required on an ATE for storing output vector data is truncation. In general, truncation involves dropping a portion of the test, i.e., a portion of the output data, mask data, and/or input data (i.e., not using this test portion in determining whether the DUT is functioning properly). As a result, the amount of data stored on the ATE may be reduced. However, truncation of vector sets (e.g., input, output, and mask vector sets), for example, also results in a reduction of test coverage, and as a consequence, may result in reduction of product quality (i.e., truncation reduces the comprehensiveness of the testing of a DUT, which may result in an improperly functioning DUT passing the test). This reduction in product quality is often not acceptable. Sometimes this technique is used in combination with vector set reordering based on the likelihood of a vector actually detecting a defect for each vector, after which the tail of the vector data is truncated. This way, the impact on test coverage can be minimized. However, in most cases there is still a significant impact on the test coverage.
One of the most attractive output compression schemes is based on signature analysis. Signature analysis is a well-known technique for compressing a sequence of logic values output from a circuit under test into a relatively small number of bits of data (signature) that, when compared to stored data (e.g., an expected signature), will indicate the presence or absence of faults in the circuit. In general, a signature of a group of output bits compresses such group of output bits and uniquely identifies such group of output bits such that it may be determined whether the group of output bits are as expected. It should be noted that there is generally a slight possibility of obtaining a correct signature for incorrect output bits (aliasing). While a signature may be used to discern whether the group of output bits is as expected, if the signature is not as expected it generally cannot be discerned from the signature which one(s) of the group of output bits had unexpected values. Thus, diagnosis of errors or error debug is generally limited (e.g., unavailable) when on-chip signature generation is used. In general, error diagnosis refers to a process for identifying an error in a DUT, such as determining the situation(s) under which the DUT has an error and/or determining the bit(s) that are incorrect as a result of the error. Error debug generally refers to a process for determining the cause of an error.
Various techniques for generating a signature for output data are well known in the art. For example, one technique comprises feeding the complete output vector data through a linear feedback shift register with different exclusive OR (XOR) feedback loops, which results in a very short signature in the shift register that depends on all output vector data. When the feedback loops, i.e. the polynomials, of the shift register are selected carefully, no significant aliasing will occur. On-chip techniques for generating a signature of the chip's output data during testing have been proposed in the existing art using circuitry called a SISR (Single Input Signature Register) or (in the case of multiple XORed inputs) a MISR (Multiple Input Signature Register). Such SISR and MISR circuitry for generating signatures on-chip are well-known in the art, and therefore are not described in greater detail herein. Examples of test schemes that use signature analysis (e.g., via a MISR) are described in the following patents: 1) U.S. Pat. No. 6,442,722 entitled “METHOD AND APPARATUS FOR TESTING CIRCUITS WITH MULTIPLE CLOCKS”, issued to Nadeau-Dostie et al.; 2) U.S. Pat. No. 6,393,594 entitled “METHOD AND SYSTEM FOR PERFORMING PSEUDO-RANDOM TESTING OF AN INTEGRATED CIRCUIT”, issued to Anderson et al.; 3) U.S. Pat. No. 6,374,370 entitled “METHOD AND SYSTEM FOR FLEXIBLE CONTROL OF BIST REGISTERS BASED UPON ON-CHIP EVENTS”, issued to Bockhaus et al.; 4) U.S. Pat. No. 6,363,506 entitled “METHOD FOR SELF-TESTING INTEGRATED CIRCUITS”, issued to Karri et al.; 5) U.S. Pat. No. 6,327,685 entitled “LOGIC BUILT-IN SELF TEST”, issued to Koprowski et al.; 6) U.S. Pat. No. 6,240,537 entitled “SIGNATURE COMPRESSION CIRCUIT AND METHOD”, issued to Sim; 7) U.S. Pat. No. 6,158,033 entitled “MULTIPLE INPUT SIGNATURE TESTING & DIAGNOSIS FOR EMBEDDED BLOCKS IN INTEGRATED CIRCUITS”, issued to Wagner et al.; 8) 5,978,946 entitled “METHODS AND APPARATUS FOR SYSTEM TESTING OF PROCESSORS AND COMPUTERS USING SIGNATURE ANALYSIS”, issued to Needham; 9) U.S. Pat. No. 5,960,008 entitled “TEST CIRCUIT”, issued to Osawa et al.; and 10) U.S. Pat. No. 5,938,784 entitled “LINEAR FEEDBACK SHIFT REGISTER, MULTIPLE INPUT SIGNATURE REGISTER, AND BUILT-IN SELF TEST CIRCUIT USING SUCH REGISTERS”, issued to Kim, the disclosures of which are hereby incorporated herein by reference. A further example of a test scheme that uses signature analysis (e.g., via a MISR) is described in U.S. Published patent application No. 20,020,073,374 entitled “METHOD, SYSTEM AND PROGRAM PRODUCT FOR TESTING AND/OR DIAGNOSING CIRCUITS USING EMBEDDED TEST CONTROLLER ACCESS DATA”, the disclosure of which is hereby incorporated herein by reference.
It should be recognized that because a signature is a compressed identification of the output bits, the amount of storage space required on an ATE for storing the output vector data (expected signatures) may be reduced well below that required for storing all of the actual expected output bits. Further, because a signature may identify an entire set of output bits (within the bounds of aliasing) desired to be analyzed (e.g., the entire output vector), test coverage is not reduced, as in the case of truncation.
However, on-chip signature analysis techniques of the existing art have several disadvantages. First, such techniques include circuitry on-chip for generating a signature of the chip's output data during testing. Such signature generation circuitry consumes area on the chip, thus increasing the overall size of the chip (or decreasing the amount of circuitry that may otherwise be included in the chip) and potentially hindering the chip's performance (e.g., because of the increased distance that signals may be required to travel given the increased size of the chip). Also, implementing the signature generation circuitry on-chip may require design modifications to be made to the circuitry under test in order to enable such signature generation circuitry to be implemented therewith. Further, the signature generation circuitry is typically utilized only during testing of the circuitry. That is, the signature generation circuitry is typically not utilized during normal operation of the circuitry in the target application. Thus, implementing the signature generation circuitry on-chip is disadvantageous in that it consumes area on the chip (thus increasing the overall size of the chip) and is useful only during-testing of the chip. Further, as mentioned above, on-chip signature generation is generally disadvantageous because it does not allow for error diagnosis (i.e., a determination as to which one(s) of a group of output bits that have incorrect outputs cannot be made from the signature of such output bits) or error debug. Further still, on-chip signature generation circuitry may itself have defects.
Additionally, since the signature depends on all output vector data, it also depends on the output vector data bits that have a non-deterministic behavior. This non-deterministic behavior can, for example, occur when a partial scan approach is used, e.g., only a subset of flip-flops on a DUT is scanned. In certain designs, some flip-flops cannot be scanned due to design constraints. Other sources of non-deterministic (unknown) output states include having multiple clock domains and tri-state buses. As a consequence, the values of these non-deterministic bits cannot be controlled without additional design modifications. However, these design modifications result in area overhead and potential performance degradation. The presence of unknown/non-deterministic output signals can corrupt the signature, making the signature and the test almost always useless. The design modifications impact on area, flow, and design performance can be a substantial disadvantage, and not acceptable for some designs.
In addition, in the on-chip signature generation techniques that do not provide on-chip masking capability, the user sometimes desires to perform only a part of the test or suppress certain non-deterministic outputs from the circuitry under test, e.g., during the debugging phase or when certain expected outputs turn out to be simulated incorrectly. In that case, depending on the number of masked outputs, signature analysis techniques of the existing art cannot be used. That is, because the signature generation techniques of the existing art comprise on-chip circuitry that is fixed for generating a signature for a certain set of output values, none of such output values can be masked out during the testing process. One could provide on-chip masking capability, however, in general extra channels/bandwidth are required to supply the masking data.
Moreover, it is very computationally intensive, and sometimes impossible, to reverse the signature analysis process. In other words, by using signature analysis techniques of the existing art, it is possible to determine a discrepancy between the actual output vector data and the expected output vector data. However, it is typically not possible to determine which received bits of the output vector data are wrong. This seriously limits the error diagnosis/debugging capability of signature-based testing methodologies of the existing art and typically requires a bypass mode for performing error diagnosis/debugging, which adds more circuitry and more inputs/outputs.
Proposals have been made for a tester that generates a signature off-chip. For example, “Low-Cost Testing of High-Density Logic Components”, IEEE Design & Test of Computers, 0740–7475 (April, 1990) proposes a tester that includes signature generation logic that receives output from a DUT and generates a signature for such received output. However, such proposed tester has several shortcomings. For instance, the proposed tester does not allow for concurrent testing and error diagnosis/debugging. Further, the proposed tester does not allow for masking out of unknown states (e.g., masking of non-deterministic output bits) in generating a signature. We are aware of no commercially available ATEs that implement the technique proposed by the “Low-Cost Testing of High-Density Logic Components” article. Further, if an ATE were implemented in accordance with such proposal, it would not allow for masking of unknown states, and if such masking were implemented it would require a substantial amount of mask data stored at the ATE (as no compression of the mask data is proposed).
Because of the above-described disadvantages, the use of signature analysis techniques to reduce the ATE memory requirements is not wide spread.